A four-layer "multilayer chip" prototype developed by engineers at Stanford University. The bottom and top layers are logic transistors, and the middle is a two-layer memory chip layer. The vertical tube is a nano-scale electronic "elevator" that connects the logic and storage layers so they can work together to solve the problem.
On the left is the current single-layer circuit card, which is separated from the memory chip in different areas and connected by wires. Just like city streets, because data is transmitted back and forth between logical areas and storage areas, congestion often occurs. On the right is a multi-layered logic chip and memory chip, forming a "skyscraper" type of chip, the data is transmitted through the nano "elevator" to achieve stereo transmission, avoiding congestion.
For decades, "smaller, faster, cheaper" has become a curse to promote the development of electronic devices. Recently, engineers at Stanford University in the United States added a fourth to the higher. At the Institute of Electrical and Electronics Engineers (IEEE) International Electronic Equipment Conference in San Francisco, USA, December 15-17, the Stanford University research team introduced how to build a "multi-layer" chip that can greatly improve current circuit card orders. Layer logic and memory chip performance.
A circuit card is like a busy city that stores data on a memory chip and calculates it through a logic chip. When the computer is busy, "digital traffic congestion" occurs on the line connecting the logic chip to the memory chip, and the "multi-layer" chip can end this congestion.
This new solution stacks logic layers on the storage layer, tightly and interconnected, and transports data between layers through thousands of nanoscale electronic "elevators" that will be connected to current single-layer logic chips and memory chips. Line speed is faster and consumes less power.
Three breakthroughs
The study was led by Sabohas Mitra and HS Philippe Weng, professors of electrical engineering and computer science at Stanford University. According to the research team, their innovation research has made three breakthroughs: the first is the new technology of manufacturing transistors, the transistor is a tiny gate, which represents 1 and 0 by switching current; the second is a new type of computer memory with multiple layers. The third is to integrate the new technology of manufacturing logic gates and memory into a new technology of multi-layer structure, which is completely different from the previous stacked chips.
“This research is still in its early stages, but our design and manufacturing techniques are scalable,†Mitra said. “With future developments, this structure will greatly improve computer performance beyond any existing computer. ."
Weng said that the prototype of this chip has been exhibited at the International Electron Devices Conference (IEDM) last year, showing how to combine logic and memory chips into a three-dimensional structure that can be mass-produced. It can be said that this changed the paradigm of the chip. "With this new structure, electronics manufacturing will turn your computer into a powerful supercomputer."
Carbon nanotubes
Engineers have built silicon chips decades ago. But whether it's a mobile phone or a tablet, it's hot, and the amount of heat released can also indicate its internal problems. Even if they are turned off, sometimes electricity leaks from the silicon transistor. Users will feel the heat, and for the system itself, this leak will also drain the battery and waste power. Researchers are working to solve this problem, such as using carbon nanotube (CNT) transistors.
Carbon nanotubes are very slender, and 2 billion roots have a hair thickness, so leakage is much less than silicon. In the second conference paper of Mitra and Weng, they introduced how they made the highest performance carbon nanotube transistors. Using the standard process of producing carbon nanotubes in the past, the density of nanotubes produced is not dense enough. They have overcome this problem and developed a flexible technology that packs enough carbon nanotubes in a small enough area to make useful chips.
They first produced carbon nanotubes on a circular quartz wafer using standard methods, then increased the thickness to a certain amount, and then peeled the entire carbon nanotube layer from the quartz medium by a bonding method and placed it on the silicon wafer. This silicon wafer is the basis of their multilayer chips.
Researchers must first create carbon nanotube layers of sufficient density to create high-performance logic devices. They repeated 13 times in this process, growing a large number of carbon nanotubes on a quartz wafer, and then peeling them off by transfer techniques to deposit them on the silicon wafer. With this simple technique to fix, they have produced some of the highest density and highest performance carbon nanotubes to date. They also demonstrate that this technique can be implemented on more than one logical layer when manufacturing multilayer chips.
"sandwich" memory
It is also important to create a high-performance CNT transistor layer that is only part of a multi-layer chip. It is also important to create a memory chip directly on each CNT transistor layer. Weng is the leader in making this kind of memory.
The new memory designed by Weng is completely different from the current memory. Instead of silicon, it uses titanium nitride, ruthenium dioxide and platinum to form a metal-oxide-metal sandwich structure. Resistance, while reverse energization, can conduct electricity. The change from resistive to conductive state is the way this new memory technology forms the numbers 0 and 1, so its name is called resistive random access memory or RRAM.
RRAM consumes less power than current memories and can be used on mobile devices to extend battery life. This new storage technology is also key to making multilayer chips because RRAM can be fabricated at lower temperatures than silicon memory.
Multilayer interconnect
The conference showed four layers of chips made by Max Scherreck and Tony Wu, graduate students of electrical engineering at Stanford University. Both the RRAM and CNT transistor layers are fabricated on a low thermal process, so the memory chip layer can be fabricated directly on each CNT logic chip. When manufacturing each memory chip layer, thousands of layers can be drilled and connected to the underlying logic layer. Small hole. On traditional circuit cards, this multi-layered interconnect allows multi-layer chips to avoid "traffic congestion."
If traditional silicon-based logic and memory chips are used, tight interconnections between layers cannot be achieved. Because it takes too much heat to make a silicon-based memory, it is about 1000 ° C, which will melt the logic chip below.
In the past, some people have studied stacked silicon chips, which saves space, but cannot avoid data "traffic congestion." Because each layer of chips is manufactured separately and connected by wires - this still tends to be congested, completely different from the "nano elevators" designed by the research team.
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